Microprocessor Program Memory

TM 11-5865-215-13

instruction (one, two or three bytes) is obtained from memory and

deposited in the CPU'S instruction register. During the execution

phase, the instruction is decoded and translated into specific process-

ing activities.

Every instruction cycle consists of from one to five machine

cycles. A machine cycle is required each time the CPU accesses

memory or an I/O port. The fetch portion of an instruction cycle

requires one machine cycle for each byte to be fetched. The duration

of the execution portion of the instruction cycle depends on the kind

of instruction that has been fetched and may vary from zero to two

machine cycles.

c. Microprocessor Program Memory. Programmer memory CCA A4 stores

all instructions (firmware) required by the microprocessor to perform

the receiver control functions. Sixteen ROM chips, each with a stor-

age capacity of 256 8-bit instruction words, provide a total of up to

4096 instruction words, or 32,768 bits of microprocessor program

memory (see figure FO-7).

The microprocessor accesses the 8-bit instruction word. by providing

a 12-bit address output during the fetch portion of the instruction

cycle. The first 8 bits provide a 1-of-256 address selection func-

tion. The upper 4 bits provide a binary 0C0 thru 0C3 code which is

translated by control CCA A7 into a memory address chip selection

signal (CS0 thru CS15). This l-of-16 memory chip selection code is

sometimes referred to as the ROM page portion of the l2-bit address.

Table 5-4 shows groups of program memory addresses with the corre-

sponding ROM chips selected on CCA A4. The resulting 8-bit output

instruction is transferred to the microprocessor during the instruc-

tion cycle fetch interval.

d. Keyboard Scan. Tile microprocessor sees the front panel key-

board as a 4-row by 11-column matrix (see figure 5-5). Each key has

its own unique matrix position for firmware identification. The ma-

trix position of the AUTO STEP key, for example, is 19 (row 1, column

9). The microprocessor scans the keyboard, four horizontal keys at a

time, starting at a group consisting of the SQL (squelch) key, TEST

TONE key, and two unused positions (matrix positions 11 thru 14), and

finishing the scan at a group consisting of the HOLD key, COARSE key,

and one unused position matrix positions 49, 4A, and 4B). Scanning

begins when the microprocessor selects output port O and sends the

following code to output port 0:

--B03

O --

--B02

O -

OB01

OB00

This code output enables matrix row 1. The microprocessor next se-

lects input port 4 to read the first four columns of row 1 via the

IB40 thru IB43 lines to see if any one of the keys has been pressed.

For this scan activity, rOWS are selected, and columns are read using

515