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Timing sequence T6
TM-11-5865-215-13 Receiver Control C-10026/USQ NSN
Miscellaneous Port Selection and Decoding
TM 11-5865-215-13
The negative pulse output of NAND gate U15B (pin 6) is applied
to line drivers U23A, U23B, and U16A via U21A and inverter U22F.  Line
drivers U23A and U23B transfer the resulting positive load pulse (at
U22F pin 12) to the receiver and SDU display, respectively.  This
pulse loads the receiver command data into decoding registers in these
units.  When a computer format has been selected, the high output of
decoder Ull inhibits these line drivers, preventing the SDU display
and receiver from loading the receiver command output.
The low CO output of format counter Ul pin 7 also enables write
timer U8 via U7C and write gate U5C.  This permits the next micro-
processor write cycle to start.
m.  Computer Update.  When the computer updates the receiver con-
trol data files, output interface CCA A5 performs the interface for
this asynchronous transfer function (see figures FO-12 and FO-13).
Line receivers U4A, U4B, and U25B transfer the computer data, a load
pulse, and clock pulses to the logic circuits on CCA A5.  Computer
input register U6 stores the 64-bit serial input (see table 5-7) for
subsequent transfer to the microprocessor files.
After the microprocessor has extracted the previous receiver com-
mand from computer input register U6, it generates an output port 6
.  This code produces a low CS6 strobe output from control CCA A7.
The CS6 strobe, or FINISHED READ signal, sets computer data input
latch U14A (pin 13).  The resulting high output inhibits NOR gate U9C,
and is inverted by U9D to produce a false (low) DATA READY,  The low
data ready signal enables EXT clock gate U9A.  The high input to U9C
(pin 9), from set latch Ul4A, provides a low enabling input to U9B
(pin 6).  The computer provides a continuous differential clock (EXT
CLOCK) which is converted into a TTL level clock by line receiver
U25A. This clock now passes through to AND gate U15D via enabled NOR
gates U9A and U9B.  U5D is enabled now by the absence of an EXT LOAD
pulse.  As a result, the EXT clock is applied to computer input regis-
ter U6.  This clock serially loads EXT DATA (computer receiver command
information) into register U6 via line receiver U4A.  The computer
shifts 64 bits of data to completely load U6, then generates an EXT
LOAD pulse.
This negative EXT LOAD pulse is applied to computer data input
latch U14A via line receiver U4B.  The latch responds by resetting.
The resulting low output (U14A-13) enables NOR gate U9C and is invert-
ed by U9D to provide a true (high) DATA READY signal. This high noti-
fies the microprocessor that new computer (receiver command) data are
In addition, the high signal inhibits EXT CLOCK gate U9A,
disabling the computer clock input path to register U6.
The microprocessor now provides a clock to transfer the 64 bits of
command data into a memory data file location designated by the A/B,
Ml, M2, M4 and M8 data within U6 (see table 5-7).  The clock is syn-
thesized by combining an input port 7 code with the corresponding IN
strobe.  CCA A7 translates the input port 7 select code into a low
CS7 signal which is applied to CCA A5.  The combined low CS7 and IN

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