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Figure 5-13. Write/Output Cycle Timing Diagram
Up
TM-11-5865-215-13 Receiver Control C-10026/USQ NSN
Next
Timing sequence T6
TM 11-5865-215-13
NOTE
Output pin 33 of CCA A5 (DATA WRITE ENABLE) is
jumpered to pin 20 (FINISHED WRITE) of CCA A5.
(3) Timing sequence T3.  The microprocessor then sends the re-
ceiver command data, four bits at a time, according to the selected
format (see figure 5-11 and FO-12).  These data are sent via the I/O
b u s . During each 4-bit character transfer, RAM U26 (on CCA A5) is
addressed via microprocessor output port 3 (by 0B30 thru 0B33) and
RAM address multiplexer U18 (on CCA A5).  The microprocessor then
generates an output port 8 code which is translated into CS8 by CCA
A 7 . The CS8 signal and the low microprocessor OUT strobe are com-
bined by OR. gate U19A (on CCA A5) to produce a write strobe.  This
strobe writes the 4-bit data on the I/0 bus into the RAM (U26) ad-
dress selected by output port 3 (OB30 thru 0B33).  The microprocessor
then changes the RAM address and repeats the sequence 15 more times
(as shown in figure 5-11) until the complete 16 character (each char-
acter = 4 bits) receiver command is written into RAM U26.
1.
Output Cycle.
(1) Timing sequence T4.  The write cycle is concluded 59 ms
after it began, when write timer U8 has counted 768 (13 kHz) clock
pulses (see figures 5-13 and FO-13).  The resulting high Q9 and Q10
outputs of U8 drive NAND gate U7D low (at pin 11).  This loW resets
write latch U14C, producing a low (U14C-10) which inhibits write gate
U5C.  The resulting low write gate output notifies the microprocessor
(via input port 7) that the write cycle is terminated, and enables the
format counter.  (The format counter does not start counting because
clock pulses have not yet been provided. )
(2) Timing sequence T5.  Twenty ms after the write latch has
been reset, the write tlmer (U8, pin 11) drives inverter U13C low at
pin 6.  This low sets output latch U14D to start the output. cycle.
The resulting high output of U14D (pin 1) switches RAM address multi-
plexer U18 so that RAM U26 is addressed by the output of format count-
ers U1 and U2 during the output cycle.  The high output also enables
clock gate U5A, providing the 5.8-kHz clock (derived from control CCA
A7) to format counters U1 and U2.  Note that the high output of output
latch U14D (pin 1) is applied to clock gate U5A and RAM address multi-
plexer U18 via internal/ external switch U7 (CLOCK IN, U17 pin 5 [Yl];
CLOCK OUT, U17 pin 3 [Y 0UT]).  In addition, the 6.5 kHz is routed to
clock gate U5A via U17 pin 14 and 13.  This clock is also constantly
applied to the computer, the receiver, and the SDU display via ,respec-
tive line drivers U16A, Ul6B, and U24A.
When enabled, clock gate U5A provides a 6.5-kHz clock drive to
the format counters.  The format counters respond to the clock by
counting down from the preset value, which was loaded by the micro-
processor format command during the previous write cycle (i.e., during
5-32

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