Miscellaneous Port Selection and Decoding

TM 1.1-5865-215-13

signals drive a functional-OR gate consisting of U13D, U13E, and U15A.

These functional-OR components respond to CS7 and the IN strobe by

producing a low clock pulse at U9C (pin 8). This clock strobe is ap-

plied to AND gate U5D (pin 13) via U9C (enabled by the low output of

reset latch 14A) and U9B (enabled by the low output of inhibited EXT

click gate U9A). Gate U5D, enabled by the absence of an EXT LOAD

pulse, transfers the microprocessor clock to register U6. U6 responds

by shifting one bit out (pin 6) and onto input port. 7 (IB70). The

microprocessor receives this bit from the I/O bus ( I/O0 line) and

loads it into the appropriate memory data file during a subsequent

instruction cycle.

A total of 64 microprocessor clocks are provided to serially trans-

fer the contents of register U6 into the designated storage location

of the memory data file. The microprocessor then generates an output

port 6 code, producing a CS6 strobe which sets computer data input

latch U14A. Set, latch U14A configures the interface logic circuits

of CCA A5 for the next 64-hit receiver command update word from the

computer.

n. Miscellaneous Port Selection and Decoding. Output interface

CCA A5 performs some receiver control -port decoding functions in ad-

dition to providing external interface (see figures 5-14 and FO-13).

These functions include:

(1) Write strobe 9, CCA A5 combines an OUT strobe with active

CS9 decoder output to produce WR9 (write strobe 9). This positive

true strobe enables I/O bus data to select a front panel frequency

display digit as shown in figure 5-14.

(2) Frequency display values. The numeric value of the digit

selected in paragraph (1) above is determined by the output port 2

drive (OB20 thru OB23) to buffers U29C thru U29F, U30A thru U30C, U21C

thru U21F, and U22A thru U22D. (Output port 2 (OB20 thru 0B23 ) data

have been latched onto those lines from respective I/0 buss I/O 0 thru

I/O 3 lines during a previous instruction cycle.) The resulting

bed-coded ABCD output lines drive the selected front panel frequency

display digit to provide the numeric value shown in table 5-8.

(3) Decimal point placement. Output port 5 provides the decimal

point placement data defined in table 5-2. The microprocessor writes

these data onto the OB50 thru OB53 lines. Buffers U21C thru U21F and

U22A thru U22D invert the l-of-4 coded output port 5 data to provide

DSO thru DS3 decimal point drive to the front panel TUNING FREQUENCY

(MHZ) display. This drive positions the decimal point according to

the code which is defined in the output port 5 column of table 5-2.

o. Miscellaneous Control and Receiver Control Clocks. Control

CCA A7 provides receiver control clock, control of panel and keyboard

lamp intensity, microprocessor power-on reset, intercom audit) output

level control, and control decoding (see figure FO-14).

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