Multiplexed A/D Converter

TM 11-5865-215-13

circuit. The multiplexed a/d converter, driven by the clock A input

(23-kHz clock from CCA A7), selects front panel CLARIFIER, MGC, and

SWEEP/STEP RATE control analog inputs, and converts these into pro-

portional binary output values. The clarifier and mgc binary data

are immediately transferred to respective output registers, while the

binary sweep/step rate data are applied to a divide-by-N counter for

frequency division control. The variable counter circuit responds to

this input by dividing the clock B input (2.9 kHz from CCA A7) by N

to provide the 90-Hz/N and 1.41 Hz/N outputs. These outputs are trans-

ferred to respective sweep rate and step rate output. registers.

The A-quad-B circuits on CCA A3 convert the dual phase output of

the MANUAL TUNING optical encoder into manual tuning rate and direc-

tion data understood by the microprocessor. The resulting manual

tuning data are applied to its output register. The microprocessor

accesses data by selecting the appropriate register, using output port

7 (1-of-4 code). Data from the selected register are transferred to

the microprocessor via input. port 2. Table 5-5 shows output port 7

codes and the corresponding register selection.

g. Multiplexed A/D Converter. The. multiplexed a/d converter cir-

cuits select one of three front panel analog control inputs, convert

this input into equivalent binary data, then store these data in the

appropriate output register (see figure FO-10 and FO-11). The multi-

plexed a/d converter consists of three basic circuit. elements which

sequentially select front panel CLARIFIER, MGC, and SWEEP/STEP RATE

inputs for conversion and storage. These three elements are the a/d

controller-timer, a/d multiplexer, and a/d converter.

(1) A/D controller-timer. The a/d controller-timer selects a/d

converter input and output data, and controls the data transfer and

data conversion phases of operation. The following sequenced opera-

tions are performed by these circuits (see figure 5-9).

(a) Timing sequence 1. At the end of a previous a/d conver-

sion operation, the start/stop gate U14B and U7D is driven low to stop

the a/d converter and enable JK flip-flops U13A, U13B, and U6B with

low reset inputs. Flip-flop U6B is set by the first clock A pulse in-

put since its JK input is held high by the Q (pin 2) output of reset

flip-flop U13B.

(b) Timing sequence 2. The resulting high Q output (pin 1)

of U6B (one clock period length) loads the binary output of the

a/d converter into the selected register.

the high output of U6B causes U13B to set.

(d) Timing sequence 4. During the next CLOCK A interval, U13A

is set in response to the high J and low K input from U13B. The

resulting high Q output of U13A15 resets U16, and drives the output of

gate stop/start U14B and U7D high via gate U22. This high immediately

resets all three flip-flops and enables the clock input to the counter

5-23