Chapter 3. FUNCTIONING OF EQUIPMENT

TM 32-5865-061-24&P

FUNCTIONING OF EQUIPMENT

` 3-1. SCOPE. This chapter provides a functional description of the Receiver Set

and its circuit card assemblies/modules to the level required for the support of

u n i t s tested by the AN/USM-410. T h e f u n c t i o n a l d e s c r i p t i o n s a r e k e y e d t o f u n c -

t i o n a l b l o c k d i a g r a m s . R e f e r to System Maintenance Manual TM 32-5865-060-24&P for

detailed system interface description.

3 - 2 . RECEIVER SET FUNCTIONAL DESCRIPTION. Refer to figure 3-1, a functional

b l o c k d i a g r a m o f t h e R e c e i v e r S e t . T h e Receiver Set provides the physical and

e l e c t r i c a l support requirements of the R-2144A/URR receivers used in the AN/MLQ-34

system. The unit can house from one to four of these receivers. With receivers

i n s t a l l e d , t h e u n i t r e c e i v e s R F a n d c o n t r o l s i g n a l s f r o m t h e s y s t e m . The RF

signals are processed by the receivers and transformed to IF and audio signals.

The unit also provides; 5 MHz reference clock signals, buffered first local

o s c i l l a t o r ( L O ) s i g n a l s a n d u n i t f a u l t s t a t u s i n f o r m a t i o n . The receivers are

digitally tuned and controlled using the data from the serial RC Bus. Figure 3-2

describes the RC Bus data format. Filter Assembly A10 is used to prevent transfer

of RF to signal and control lines. These functions are described in the following

subparagraphs.

3 - 2 . 1 I n p u t S i g n a l s . A single receiver control bus (RC Bus) controls all four

The RC bus provides DATA, CLOCK, and STROBE signals. These are

receivers.

j u m p e r e d through A9. T h i s i s t o a l l o w f o r a s e p a r a t e c o n t r o l s o u r c e f o r

receiver 1 should this be required. Each receiver requires a 6-bit address

i n p u t . The location of a receiver within the Receiver Set is determined by the

three low order bits of the address hard wired at the rear connector. The three

high order bits, (Receiver Set address), are determined by signals which are part

o f the RC bus. R F s i g n a l s a r e f e d t o e a c h r e c e i v e r . T h e 5 M H z r e f e r e n c e o s c i l -

lator, Y1, produces a 5 MHz clock signal. This signal is routed out, 5 MHz REF

OUT, and back to the unit through a jumper to buffer amplifier A5. The reference

signal is buffered and then applied to each receiver.

3-2.2 Receiver Output Signals. Each receiver provides the following signals

which are interfaced to the system through connectors on the rear of the Receiver

Set:

a . Wideband IF (WBIF)

b . Narrowband IF (NBIF)

c. AUDIO, standard and auxiliary

d. Analog automatic gain control (AGC)

e . First LO output (STEP LO). Solid state amplifiers, AR1 through AR4, buffer

and amplify the signals from the receiver before they are output from the unit.