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Figure 5-10. Manual Tuning Timing Diagram
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TM-11-5865-215-13 Receiver Control C-10026/USQ NSN
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Figure 5-11. Receiver Command Output Format
TM 11-5865-215-13
J.
External Interface.  Output interface CCA A5 performs those
functions necessary to transfer receiver command data from the data
A/data B files (part of microprocessor RAM storage) to external de-
vices (see figure FO-12).
In addition, CCA A5 accepts receiver com-
mand data from the external device and stores this information in the
microprocessor data files.  This data file update procedure is per-
formed prior to a mission, or in the event the receiver control loses
power and dumps its data file memory.
CCA A5 provides the timing that alternately produces the write and
output cycles.  An output cycle formats and generates the serial 51-
bit receiver/SDU command data or the 64-bit computer command data. A
write cycle, which involves retrieving the command data from the micro-
processor files and storing this information temporarily, is initiated
at the conclusion of the output cycle.
Logic circuits on CCA A5 respond to the completed output cycle by
generating a high DATA WRITE ENABLE signal.  This high, transfixed
via the IB70 line, causes the microprocessor to first send a format
command, then write the receiver command data, four bits at a time,
into a RAM on CCA A5.  The two selectable formats are the receiver/SDU
format (51 bits), and computer format (64 bits).  The receiver control
normally uses the receiver/SDU format. unless a receiver command in the
microprocessor files has been modified.  In that event a computer for-
mat is selected so that the ensuing output cycle will update the com-
puter memory.  Sixteen 4-bit characters are written into the CCA A5
RAM as shown in figure 5-11.  CCA A5 logic circuits provide 134 ms of
time for this write cycle to be executed
When the write cycle time expires, the output cycle is started.
Data stored (written) in the RAM are retrieved and formatted into a
51-bit or 64-bit. word (depending on the format previously selected),
which is output to the receiver, SDU display, or the computer. In
addition, CCA A5 provides clock pulses to shift the serial data word
and a load pulse at the end of the shift operation.  Concurrent. with
generation of the load pulse  ,CCA AS goes back into the write mode of
operation.
When the computer is required to refresh the microprocessor data
files, it clocks the serial 64-bit receiver command data into the com-
puter input register on CCA A5 (see figure 5-12).  Then a load pulse
is applied to the TEST signal line, notifying the microprocessor that
the register is loaded.  The microprocessor responds by shifting the
data from the computer input register (on CCA A5) into the appropriate
microprocessor data file.  At the conclusion of this operation the
microprocessor sends a FINISHED READ signal, which permits the com-
puter to send the next receiver command.
k.  Write Cycle.  RAM U26, on output interface CCA A5, permits
temporary storage of the receiver command data from microprocessor
files during the write cycle.  The write cycle, initiated at the con-
clusion of a previous output cycle, is executed in the following
manner (see figures 5-13 and FO-13):
5-28

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