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Figure 5-9. Multiplexed A/D Conversion Timing Diagram
Up
TM-11-5865-215-13 Receiver Control C-10026/USQ NSN
Next
Sweep/Step Rate Data Generation
TM 11-5865-215-13
U16 via U14.
In addition, the high transition of the start/stop
gate clocks the a/d multiplexer, selecting the next analog input for
conversion.
(2) A/D multiplexer.  The a/d multiplexer consists of input
switch U15, output register select gate U23, and decimal counter U12.
Decimal counter U12 responds to the clocking input from the a/d
controller-timer circuits by sequentially going high at the 0 output,
then at the 1 output, then at the 2 output.  These outputs cause
switch U15 to select the analog inputs from the front panel controls
for a/d conversion.  The resulting binary data output of the a/d con-
verter is transferred to an output register also selected by the dec-
imal counter output.  Output register select gate U23 responds to an
enabling input from the a/d controller-timer, as well as the decimal
counter output, by routing the a/d output to the appropriate register.
Table 5-6 lists the three states of decimal counter U12 and the corre-
sponding input data and output register selections.
(3) A/D converter.  The a/d conversion function consists of data
conversion and data transfer phases of operation (see figure FO-11).
Data conversion occurs after the previously processed data have been
transferred to a selected output register for storage.  A pulse from
a/d controller-timer U13A-15) clears the a/d converter, selects the
next analog input, and imitiates the next conversion operation (see
figure 5-9).  The key a/d converter components are voltage comparator
U19 , start/stop gate U14B and U7D, clock gate U14D, binary counter
U16, feedback digital-to-analog (d/a) converter U20, and limit gate
U22.
Voltage comparator Ul9 compares the analog input voltage with the
voltage input from feedback d/a) converter U20.  Since the a/d con-
verter is initially cleared, the feedback voltage is approximately
O V.  U19 responds to the higher analog input voltage by going high
at output pin 7.  This output drives the output of start/stop gate
U14B/U7D high, enabling (clock gate U14D.  Enabled, U14D provides
CLOCK A pulses which are counted by binary counter U16.  The result-
ing 6-bit binary output drives feedback d/a converter U20 via invert-
er U21.  Converter U20 increases its output voltage by an amount pro-
portional to the increasing binary count.  This output voltage is the
feedback input to voltage comparator U19.  When the binary count
causes the feedback to reach the level of the analog input, the volt-
age comparator output goes low.  This low inhibits the clock input to
the binary counter via the start/stop gate.  In addition, the low
output enables the a/d controller-timer circuits, which then initiate
the data transfer phase of operation.  At this point the 6-bit output
of the binary counter is a value equivalent to the analog input at
the voltage comparator.  If, as a result of some failed circuit, the
analog signal level is too high, the binary counter output is driven
to a level of 63 (llllll)).  Limit gate U22 then responds by going
low to inhibit further counting and terminates the a/d conversion
phase of operation.
525

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