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Table 5-3. Microprocessor Strobes
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TM-11-5865-215-13 Receiver Control C-10026/USQ NSN
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Figure 5-3. Microprocessor Functional Block Diagram
TM 11-5865-215-13
Section III.
DETAILED FUNCTIONING OF EQUIPMENT
Introduction.
This section provides detailed theory of operation for the receiver
control.  Figure FO-5 is a functional block diagram of the receiver
control.
Detailed Description,
a.  Microprocessor Orqanization.  Microprocessor CCA Al is basic-
ally an 8-bit character system using an interface for retrieving in-
structions from program memory and controlling data exchange with the
receiver control peripheral circuits (see figures 5-3 and FO-6).  The
three basic components of the microprocessor are the central control
unit (CPU), RAM memory, and a microprocessor interface.  Communication
between the CPU, RAM memory, and the microprocessor interface is ac-
complished with a 4-bit internal bus.
(1) CPU.
The CPU performs the operations necessary to define
and transfer the front panel receiver control commands Or to read
receiver command inputs from the computer.
These operations are
synchronized by a 1.67-MHz clock in accordance with instructions
retrieved from programmer memory CCA A4.
(2) RAM memory.  The RAM memory is the storage space or scratch-
pad where data are written or read by the CPU while executing program
instructions.  In addition, the RAM memory provides storage space for
data file A and B information.  The data file portion of the RAM
memory consists of twenty 64-bit receiver commands.  A total of 256
bytes, or 2048 bits may be written into, or read out of, RAM memory.
(3) Microprocessor interface.  The interface allows the CPU to
communicate with the peripheral receiver control circuits, as well as
with programmer memory CCA A4.  A 12-bit address (eight address bits
and four chip-select bits) is output by the CPU and applied. to the
program memory via the 8-bit address bus (0A0 thru 0A7) and control
CCA A7.  The resulting 8-bit instruction output of the program memory
is applied to the interface via instruction bus IDO thru ID7 lines.
The CPU then selects a peripheral. circuit with a 4-bit character on
the interface 0C0 thru 0C3 lines, activates the IN or OUT strobe (de-
fining an input or output port), and reads or writes the data via a
selected port or the bidirectional I/O bus.
b.  Microprocessor Timing.  The microprocessor CPU uses a two-phase,
1.67-MHz clock (see figure 5-4).  Four to 18 clock cycles make up an
instruction cycle.  During the first two clock cycles, the micro-
processor generates a sync pulse to mark the beginning of the instruc-
tion cycle.  An instruction cycle is defined as the time required to
fetch and execute an instruction.  During the fetch, a selected

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